Cascode bias of power MOS transistors

Cascode bias of power MOS transistors

There is disclosed a driver circuit for a power amplifier of class D type having a segmented architecture with at least one current branch (22) which can be powered down in a low power mode of operation of the circuit. The branch comprising a switch with a cascode MOS transistor, the circuit further...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Allier, Emmanuel, Amiard, François, Binet, Vincent
Format: Patent
Sprache:eng ; fre ; ger
Schlagworte:
AMPLIFIERS
BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
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Beschreibung
Zusammenfassung:There is disclosed a driver circuit for a power amplifier of class D type having a segmented architecture with at least one current branch (22) which can be powered down in a low power mode of operation of the circuit. The branch comprising a switch with a cascode MOS transistor, the circuit further comprises a bias circuitry (31N, 31P) adapted for dynamically generating a dynamic bias control signal (DyncascN, DyncascP) so as to cause the cascode MOS transistor of the switch to be 'Off' in the low power mode.