Field effect transistor and related devices

A fin Field Effect Transistor (finFET) arrangement according to the invention can includes a source region and a drain region of the finFET, as well as a gate of the finFET crossing over a fin of the finFET between the source and drain regions. First and second silicide layers are formed on the source and drain regions respectively. The first and second silicide layers include respective first and second surfaces that face the gate crossing over the fin, where the first and second surfaces have different sizes.