Output buffer and signal processing method

An output buffer comprises a series connection of a first field effect transistor (MN0) and a second field effect transistor (MP0), wherein the first field effect transistor is connected to a first supply potential terminal (GND) and the second field effect transistor is connected to a second supply potential terminal (VDD). An output terminal (T-OUT) is connected to a common connection of the first transistor and the second transistor. The output buffer has a series connection of a resistive element (R1) and a capacitive element (C1), wherein the capacitive element is connected to the output terminal, and a control circuit (CTRL), to which an input signal (INP) is provided. The control circuit controls the transistors in such a way that turning off of a transistor is performed immediately, while turning on of a transistor is performed depending on the charging or discharging of the capacitive element, thus achieving a defined slew rate of the output signal at the output terminal.