INDUCED THERMAL GRADIENTS

An apparatus comprising: a semiconductor die including: a first thermal sensor and a second thermal sensor, the first and second thermal sensors to detect a thermal gradient, and logic circuitry to provide a thermal offset bit to a storage location for the thermal offset bit of a mode register of a memory die responsive to detection of a change in the thermal gradient, the memory die including dynamic random access memory (DRAM); wherein the thermal offset bit is to direct a temperature compensated self-refresh (TCSR) logic of the memory die to modify a self-refresh rate of the DRAM; wherein the first thermal sensor is to be aligned with or in close proximity with a memory thermal sensor of the memory die, and wherein the second thermal sensor of the semiconductor die is located at a hot spot of the semiconductor die.