METHOD OF FABRICATING A LATTICE-MISMATCHED SEMICONDUCTOR STRUCTURE WITH REDUCED DISLOCATION DEFECT DENSITIES

METHOD OF FABRICATING A LATTICE-MISMATCHED SEMICONDUCTOR STRUCTURE WITH REDUCED DISLOCATION DEFECT DENSITIES

Fabrication of monolithic lattice-mismatched semiconductor heterostructures with limited area regions having upper portions substantially exhausted of threading dislocations, as well as fabrication of semiconductor devices based on such lattice-mismatched heterostructures.

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Bibliographische Detailangaben
Hauptverfasser: Lochtefeld, Anthony J, Currie, Matthew T, Fiorenza, James, Langdo, Thomas A, Braithwaite, Glyn, Cheng, Zhiyuan
Format: Patent
Sprache:eng ; fre ; ger
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:Fabrication of monolithic lattice-mismatched semiconductor heterostructures with limited area regions having upper portions substantially exhausted of threading dislocations, as well as fabrication of semiconductor devices based on such lattice-mismatched heterostructures.