A PARALLEL MULTI-PIPELINE SYSTOLIC ARRAY FOR COMPLEX SINGULAR VALUE DECOMPOSITION ON A MULTI-PROCESSOR DEVICE

The present invention refers to the field of wireless communications and more specifically to the design of a Parallel Multi-Pipeline Systolic Array (PMSA) architecture that implements Complex Singular Value Decomposition (CSVD) on a multi-processor device. CSVD is an important matrix factorization technique of a complex matrix P into a product of three matrices, i.e. a Hermitian unitary matrix of eigenvectors U, a diagonal matrix of eigenvalues S and a matrix of eigenvectors V, with several applications in Digital signal processing and wireless communications. The apparatus to perform the CSVD includes n sets of blocks, with n being a multiple of three, with each set of blocks comprising a first hardware block (60, 13), a second hardware block (70, 14) other than the first hardware block and a third hardware block (15) other than the first hardware block and the second hardware block; whereby a) the first hardware block (60, 13) of each of the n sets of blocks includes means to transform a 2x2 square matrix to a 2x2 upper triangular square matrix, b) the second hardware block (70, 14) of each of the n sets of blocks includes means to transform a 2x2 upper triangular matrix to a to a 2x2 diagonal square matrix c) the third hardware block (15) of each of the n sets of blocks includes means to swap and exchange elements of matrices. Further the apparatus includes means to transmit the output of the i-th set of blocks, with i equals 1 to n-1, to the i+1 set of blocks, and means to process a plurality of consecutive matrices simultaneously.