Multi-level sigma-delta ADC with reduced quantization levels

The invention relates to a multi-level sigma-delta Analog-to-Digital converter 200 comprising: - a direct path (d1) having an input terminal (Id1) to receive an input analog signal (X) and an output terminal (Od1) to provide a output digital signal (Y) corresponding to said input analog signal (X), said direct path (d1) comprising: - a computation block (S2) arranged to receive a first analog signal (X1) representative of the input analog signal (X) and to provide a analog computed signal (X2); - an analog integrator (2) having an input terminal (12) operatively associated to the computation block (S2) to receive the analog computed signal (X2) and a output terminal (02) to provide a third analog signal (X3), - a quantizer (3) having a respective input terminal (13) operatively connected to the output terminal (02) of the analog integrator (2) and a respective output terminal (03) operatively connected to the output terminal (Od1) of the direct path (d1). The converter (200) is characterised in that it comprises a first feedback path (f1) arranged to provide to the computation block (S2) a feedback analog signal (AN1) representative of a digital signal (DS) present at the output terminal (03) of the quantizer (3), said computation block (S2) being arranged to subtract said feedback analog signal (AN1) from the first analog signal (I1), said first feedback path (f1) comprising an amplification block (A0) having a respective gain factor (1/K2). Furthermore, the converter (200) is characterised in that the direct path (d1) comprises a first amplification block (A2) interposed between said computational block (S2) and the input terminal (13) of the quantizer (3; 3'), said first amplification block (A2) of the direct path (d1) having a respective gain factor (K2) which is the inverse of the gain factor (1/K2) of the amplification block (A0) of the first feedback path (f1).