Method of fabricating a high-voltage transistor

A method for making a high voltage insulated gate field-effect transistor with one or more JFET conduction channels comprises successively implanting a dopant (64) of a first conductivity type in a first epitaxial layer (60) of a second conductivity type so as to form a first plurality of buried layers (65) disposed at a different vertical depth. A second epitaxial layer (70) of the first conductivity type is formed on the first epitaxial layer and the implant process repeated to form a second plurality of buried layers (75) in stacked parallel relationship to the first plurality of buried layers.