Frequency division
A frequency divider (100) comprises a signal generation stage (110) arranged to employ a clock at a clock frequency to provide a first reference signal and a second reference signal, the second reference signal corresponding to the first reference signal delayed by half a period of the clock signal....
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| Format: | Patent |
| Sprache: | eng ; fre ; ger |
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| Zusammenfassung: | A frequency divider (100) comprises a signal generation stage (110) arranged to employ a clock at a clock frequency to provide a first reference signal and a second reference signal, the second reference signal corresponding to the first reference signal delayed by half a period of the clock signal. A synchronisation stage (120) is arranged to generate an output signal having an output frequency divided from the clock frequency by switching between the first reference signal and the second reference signal once per cycle of the output signal. |
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