Power optimization when using external clock sources

Logic circuits of a digital device may be biased to operate over specific external clock frequency ranges by programming a desired clock oscillator frequency range into a configuration memory of the digital device. In addition, clock source selection may also be programmed into the configuration register. Bias circuits are then configured so that the internal logic of the digital device will operate over the desired clock oscillator frequency range. Non-volatile memory may be used to store the contents of the configuration memory so as to retain the configuration during power down of the digital device. The non-volatile memory may be programmable fuse links, electrically erasable and programmable memory (EEPROM), FLASH memory, etc.