Configurable filter and receiver incorporating same

An efficient configurable signal filter (52). The filter (52) includes a first mechanism for receiving a first signal of a first type and a second signal of a second type. A second mechanism (60, 62) selectively filters the first signal during a first mode of operation and filters the second signal during a second mode of operation. A third mechanism (68) generates control signals. A fourth mechanism (64, 68) automatically configures the second mechanism (60, 62) to operate in the first mode of operation or the second mode of operation based on the control signals. In a specific embodiment, the first type of signal is characterized by a first rate, and the second type of signal is characterized by second rate. The first signal and second signal are digital ADC outputs. The second mechanism (60, 62) includes plural filter blocks (60, 62), each having one or more Multiply-Accumulate (MAC) blocks. Each of the one or more MAC blocks include one or more MAC pipes that are each associated with a coefficient memory data structure of a coefficient memory (64). The third mechanism (68) or a user selects coefficients from each memory data structure to apply to each MAC block, thereby selectively affecting filter response. The control signals direct multiplexers or switches to configure the MAC pipes in a serial configuration or a parallel configuration corresponding to the first mode of operation or the second mode of operation, respectively.