Package substrate unit and method for manufacturing package substrate unit

A semiconductor chip mounting layer (20) of a package substrate unit (1) includes an insulation layer (21), a conductive seed metal layer (22a) formed on the top surface of the insulation layer (21), conductive pads (23) formed on the top surface of the conductive seed metal layer (22a), metal posts...

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Bibliographische Detailangaben
Hauptverfasser:	TAKAHASHI, YASUHITO, FUKUI, KEI, YOSHIMURA, HIDEAKI, ARAI, KAZUYA, IKEGAMI, SHINPEI, NANG, HNIN NWAY SAN, SUZUKI, HITOSHI
Format:	Patent
Sprache:	eng ; fre ; ger
Schlagworte:	BASIC ELECTRIC ELEMENTS CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS CLADDING OR PLATING BY SOLDERING OR WELDING CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ELECTRICITY GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS MACHINE TOOLS MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS METAL-WORKING NOT OTHERWISE PROVIDED FOR PERFORMING OPERATIONS PRINTED CIRCUITS SEMICONDUCTOR DEVICES SOLDERING OR UNSOLDERING TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION TECHNICAL SUBJECTS COVERED BY FORMER USPC TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS TRANSPORTING WELDING WORKING BY LASER BEAM
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Beschreibung
Zusammenfassung:	A semiconductor chip mounting layer (20) of a package substrate unit (1) includes an insulation layer (21), a conductive seed metal layer (22a) formed on the top surface of the insulation layer (21), conductive pads (23) formed on the top surface of the conductive seed metal layer (22a), metal posts (24) formed substantially in the central portion on the top surface of the conductive pads (23), and a solder resist layer (25) that is formed to surround the conductive pads (23) and the metal posts (24).