SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR PACKAGE MOUNTING STRUCTURE

The semiconductor package 1 includes a package wiring board 2 having an element housing recessed portion 2a on its top surface to house a semiconductor element 3; multiple side electrodes 7 which are arranged on the outer side surface of the package wiring board 2 and soldered to multiple motherboar...

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Bibliographische Detailangaben
Hauptverfasser: SHIRASE, TAKASHI, HAMAGUCHI, TSUNEO, SUGIURA, IKIO, IWATA, MASAKI, SAKAMOTO, HIROO, OKAMURO, TAKASHI
Format: Patent
Sprache:eng ; fre ; ger
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Zusammenfassung:The semiconductor package 1 includes a package wiring board 2 having an element housing recessed portion 2a on its top surface to house a semiconductor element 3; multiple side electrodes 7 which are arranged on the outer side surface of the package wiring board 2 and soldered to multiple motherboard electrodes 8 arranged on a motherboard 10; a semiconductor element fixed onto the bottom surface of the element housing recessed portion 2a; and an element electrode 5 arranged on the bottom of the element housing recessed portion 2a and electrically connected to the semiconductor element 3 and the side electrodes 7. The package wiring board 2 has a multilayered structure in which woven fabric 21 and a resin adhesive layer 22 are alternately laminated, and the resin adhesive layer 22 is formed of a resin adhesive that contains inorganic filler particles. In this manner, cracks are suppressed in the soldered portion in an environment in which rise and fall of temperature are repeated, and the soldering reliability can be improved.