UTILIZING A BIDDING MODEL IN A MICROPARALLEL PROCESSOR ARCHITECTURE TO ALLOCATE ADDITIONAL REGISTERS AND EXECUTION UNITS FOR SHORT TO INTERMEDIATE STRETCHES OF CODE IDENTIFIED AS OPPORTUNITIES FOR MICROPARALLELIZATION

Bibliographische Detailangaben

1. Verfasser:	LOEN, LARRY, WAYNE
Format:	Patent
Sprache:	eng ; fre ; ger
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
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