Memory cells having a row-based read and/or write support circuitry

A circuit comprises a plurality of memory cells (110) in a row, at least one write word line (WWL), and a write support circuit (120) coupled to the at least one write word line and to the plurality of memory cells in the row. The write support circuit includes a first current path (transistor N7 of 120) and at least one second current path (diode D of 120). A current path of the at least one second current path corresponds to a respective write word line of the at least one write word line. A write word line of the at least one write word line is configured to select the first current path when the plurality of memory cells in the row operates in a first mode, and to select a second current path of the at least one second current path when the plurality of memory cells in the row operates in a second mode.