METHOD AND APPARATUS FOR PROTECTING TRANSISTORS

The invention relates to a method and to an apparatus for protecting transistors (S1, S3; S2, S4) arranged in at least one path, wherein transistors (S1, S3; S2, S4) connected in series to which an input voltage (Ue) is applied are arranged in a path (2), and the transistors (S1, S3; S2, S4) of a pa...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: ACHLEITNER, GUENTER, HOLZINGER, STEPHAN, PAMMER, WALTER, PIRCHENFELLNER, JUERGEN
Format: Patent
Sprache:eng ; fre ; ger
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Beschreibung
Zusammenfassung:The invention relates to a method and to an apparatus for protecting transistors (S1, S3; S2, S4) arranged in at least one path, wherein transistors (S1, S3; S2, S4) connected in series to which an input voltage (Ue) is applied are arranged in a path (2), and the transistors (S1, S3; S2, S4) of a path are alternately switched between a conductive state and a blocking state in order to generate an output voltage (Ua) at the center of the path. In order to prevent both transistors (S1, S3; S2, S4) of a path from triggering, the blocking state of the second transistor (S3; S4) of the path is checked before switching a transistor (S1; S2) into the conductive state, and the switching is released by way of a signal generated during the check.