Press-pack module with power overlay interconnection

Systems and methods for utilizing power overlay (POL) technology and semiconductor press-pack technology to produce semiconductor packages (50, 70, 78, 80, 90, 100, 110, 120) with higher reliability and power density are provided. A POL structure (40) may interconnect semiconductor devices (48) within a semiconductor package (50, 70, 78, 80, 90, 100, 110, 120), and certain embodiments may be implemented to reduce the probability of damaging the semiconductor devices (48) during the pressing of the conductive plates (58, 60). In one embodiment, springs (54) and/or spacers (56) may be used to reduce or control the force applied by an emitter plate (58) onto the semiconductor devices (48) in the package (50, 70, 78, 80, 90, 100, 110, 120). In another embodiment, the emitter plate (58) may be recessed to exert force on the POL structure (40), rather than directly against the semiconductor devices (48). Further, in some embodiments, the conductive layer (42) of the POL structure (40) may be grown to function as an emitter plate (58), and regions of the conductive layer (40) may be made porous to provide compliance.