Semiconductor device with a drain region underlying a gate contact pad
The present invention relates to a semiconductor device and has an object to enhance a di / dt tolerance and a dV / dt tolerance without increasing an ON resistance. In order to achieve the object described above, the semiconductor device has a peripheral base region (21) formed in a drain layer (3)...
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| Format: | Patent |
| Sprache: | eng ; fre ; ger |
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| Zusammenfassung: | The present invention relates to a semiconductor device and has an object to enhance a di / dt tolerance and a dV / dt tolerance without increasing an ON resistance.
In order to achieve the object described above, the semiconductor device has a peripheral base region (21) formed in a drain layer (3) of opposite conductivity type. Said peripheral base region may be coupled to one end of regions of a main base region (4). |
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