Press-fit diode resistant to changes in temperature
The diode has a semiconductor chip attached between a base and a head-wire (6) by a solder layer (5) and closing a PN-transition (30) at an outer edge of the chip. The solder layer in an outer region is variably removed relative to the outer edge, where the region is at short distance from the PN-tr...
Gespeichert in:
Hauptverfasser: | , , , |
---|---|
Format: | Patent |
Sprache: | eng ; fre ; ger |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | Jaros, Rolf Suelzle, Helmut Goerlach, Alfred Spitz, Richard |
description | The diode has a semiconductor chip attached between a base and a head-wire (6) by a solder layer (5) and closing a PN-transition (30) at an outer edge of the chip. The solder layer in an outer region is variably removed relative to the outer edge, where the region is at short distance from the PN-transition. An insulation layer (10) with a combination of oxide and silicon nitride is provided over a solderless region of the chip, and a Schottky diode e.g. trench-junction-barrier-Schottky diode and trench-metal oxide semiconductor (MOS)-barrier-Schottky diode, is provided within the chip. |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_EP2381473B1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>EP2381473B1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_EP2381473B13</originalsourceid><addsrcrecordid>eNrjZDAOKEotLtZNyyxRSMnMT0lVAHIzi0sS80oUSvIVkjMS89JTixUy8xRKUnMLUosSS0qLUnkYWNMSc4pTeaE0N4OCm2uIs4duakF-fGpxQWJyal5qSbxrgJGxhaGJubGToTERSgCp_iwc</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Press-fit diode resistant to changes in temperature</title><source>esp@cenet</source><creator>Jaros, Rolf ; Suelzle, Helmut ; Goerlach, Alfred ; Spitz, Richard</creator><creatorcontrib>Jaros, Rolf ; Suelzle, Helmut ; Goerlach, Alfred ; Spitz, Richard</creatorcontrib><description>The diode has a semiconductor chip attached between a base and a head-wire (6) by a solder layer (5) and closing a PN-transition (30) at an outer edge of the chip. The solder layer in an outer region is variably removed relative to the outer edge, where the region is at short distance from the PN-transition. An insulation layer (10) with a combination of oxide and silicon nitride is provided over a solderless region of the chip, and a Schottky diode e.g. trench-junction-barrier-Schottky diode and trench-metal oxide semiconductor (MOS)-barrier-Schottky diode, is provided within the chip.</description><language>eng ; fre ; ger</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2018</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20181003&DB=EPODOC&CC=EP&NR=2381473B1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20181003&DB=EPODOC&CC=EP&NR=2381473B1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Jaros, Rolf</creatorcontrib><creatorcontrib>Suelzle, Helmut</creatorcontrib><creatorcontrib>Goerlach, Alfred</creatorcontrib><creatorcontrib>Spitz, Richard</creatorcontrib><title>Press-fit diode resistant to changes in temperature</title><description>The diode has a semiconductor chip attached between a base and a head-wire (6) by a solder layer (5) and closing a PN-transition (30) at an outer edge of the chip. The solder layer in an outer region is variably removed relative to the outer edge, where the region is at short distance from the PN-transition. An insulation layer (10) with a combination of oxide and silicon nitride is provided over a solderless region of the chip, and a Schottky diode e.g. trench-junction-barrier-Schottky diode and trench-metal oxide semiconductor (MOS)-barrier-Schottky diode, is provided within the chip.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2018</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDAOKEotLtZNyyxRSMnMT0lVAHIzi0sS80oUSvIVkjMS89JTixUy8xRKUnMLUosSS0qLUnkYWNMSc4pTeaE0N4OCm2uIs4duakF-fGpxQWJyal5qSbxrgJGxhaGJubGToTERSgCp_iwc</recordid><startdate>20181003</startdate><enddate>20181003</enddate><creator>Jaros, Rolf</creator><creator>Suelzle, Helmut</creator><creator>Goerlach, Alfred</creator><creator>Spitz, Richard</creator><scope>EVB</scope></search><sort><creationdate>20181003</creationdate><title>Press-fit diode resistant to changes in temperature</title><author>Jaros, Rolf ; Suelzle, Helmut ; Goerlach, Alfred ; Spitz, Richard</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_EP2381473B13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; fre ; ger</language><creationdate>2018</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Jaros, Rolf</creatorcontrib><creatorcontrib>Suelzle, Helmut</creatorcontrib><creatorcontrib>Goerlach, Alfred</creatorcontrib><creatorcontrib>Spitz, Richard</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Jaros, Rolf</au><au>Suelzle, Helmut</au><au>Goerlach, Alfred</au><au>Spitz, Richard</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Press-fit diode resistant to changes in temperature</title><date>2018-10-03</date><risdate>2018</risdate><abstract>The diode has a semiconductor chip attached between a base and a head-wire (6) by a solder layer (5) and closing a PN-transition (30) at an outer edge of the chip. The solder layer in an outer region is variably removed relative to the outer edge, where the region is at short distance from the PN-transition. An insulation layer (10) with a combination of oxide and silicon nitride is provided over a solderless region of the chip, and a Schottky diode e.g. trench-junction-barrier-Schottky diode and trench-metal oxide semiconductor (MOS)-barrier-Schottky diode, is provided within the chip.</abstract><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | eng ; fre ; ger |
recordid | cdi_epo_espacenet_EP2381473B1 |
source | esp@cenet |
subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | Press-fit diode resistant to changes in temperature |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-07T03%3A53%3A39IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Jaros,%20Rolf&rft.date=2018-10-03&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EEP2381473B1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |