System on chip breakpoint methodology

A system-on-chip (SoC) with a debugging methodology. The system-on-chip (SoC) includes a central processing unit (CPU) (101) and multiple computing elements connected to the CPU (101). The CPU (101) is configured to program the computing elements (109) with task descriptors (21) and the computing elements (109) are configured to receive the task descriptors (21) and to perform a computation based on the task descriptors. The task descriptors (21) include a field (203) which specifies a breakpoint state of the computing element (109). A system level event status register (ESR) (301) attaches to and is accessible by the CPU (101) and the computing elements (109). Each of the computing elements (109) has a comparator configured to compare the present state of the computing element (109) to the breakpoint state. The computing element (109) is configured to drive a breakpoint event to the event status register (ESR) (301) if the present state of the computing element (109) is the breakpoint state. Each of the computing elements (109) has a halt logic unit operatively attached thereto, wherein the halt logic unit is configured to halt operation of the computing element (109). The ESR (301) is configurable to drive a breakpoint event to the halt logic units to halt at least one of the computing elements (109) other than the computing element (109) driving the breakpoint event.