A synchronization system and related integrated circuit

A synchronization system comprising a memory (12) and a control circuit (20). The control circuit (20) comprises: - a write interface for writing data in said memory (12) with a first clock signal, wherein the write interface is configured for operating with a write pointer in response to a write co...

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Bibliographische Detailangaben
Hauptverfasser:	GUARNACCIA, GIUSEPPE, GUARRASI, RAFFAELE, KACEM, RADHIA
Format:	Patent
Sprache:	eng ; fre ; ger
Schlagworte:	CALCULATING CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION ANDCOMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION ANDCOMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWNENERGY USE COMPUTING COUNTING ELECTRIC COMMUNICATION TECHNIQUE ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS PHYSICS TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINSTCLIMATE CHANGE TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
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Beschreibung
Zusammenfassung:	A synchronization system comprising a memory (12) and a control circuit (20). The control circuit (20) comprises: - a write interface for writing data in said memory (12) with a first clock signal, wherein the write interface is configured for operating with a write pointer in response to a write command, - a read interface for reading data from said memory (12) with a second clock signal, wherein the read interface is configured for operating with a read pointer in response to a read command, and - a synchronization circuit for synchronizing said write pointer and said read pointer with a synchronization latency. An elaboration circuit (30) is also provided for elaborating data in memory (12) with an elaboration latency, wherein the elaboration latency is smaller than the synchronization latency.