Architecture using integrated backup control and protection hardware

Architecture using integrated backup control and protection hardware

An electronic control configuration (10a) includes at least one secondary microprocessor (32a, 32b) operable to control a device (12). The at least one secondary microprocessor (32a, 32b) assumes protection control of the device responsive to a first type of failure by transmitting a protection cont...

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Bibliographische Detailangaben
Hauptverfasser: KAMENETZ, JEFFRY K, HARTMAN, JAY H, ROY, KEVIN P, FISCHER, STEVEN R, BETTERINI, WILLIAM, KOKAS, JAY W, DI VINCENZO, GREGORY, ORSINI, LUKE J, JOHNSTON, MARK A
Format: Patent
Sprache:eng ; fre ; ger
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Zusammenfassung:An electronic control configuration (10a) includes at least one secondary microprocessor (32a, 32b) operable to control a device (12). The at least one secondary microprocessor (32a, 32b) assumes protection control of the device responsive to a first type of failure by transmitting a protection control signal to a first effector (18). The at least one secondary microprocessor (32a, 32b) assumes backup control of the device responsive to a second type of failure by transmitting a backup control signal to a second effector (16). The backup control functionality of the at least one secondary microprocessor (32a, 32b) can be selectively disabled.