METHOD OF FORMING NAND UNIT CELLS

A semiconductor construction comprises a NAND memory array having wordlines and intersecting local bitlines. The construction comprises unit cells having NAND strings extending vertically relative to a supporting semiconductor substrate. Each NAND string has a plurality of control gate structures including charge-trapping transistor devices located at intersections of the wordlines and local bitlines. The charge trapping devices of each NAND string are connected in series, source to drain, between a source selecting control gate device and a drain selecting control gate device. The source selecting control gate device is located at an intersection of a local bitline and a source select line and the drain selecting control gate device is located at an intersection of a local bitline and a drain select line. The control gate structures are each part of conductive lines extending in a first direction, the conductive lines extending beyond the NAND unit cells to form a series of steps with exposed platforms. A plurality of electrical interconnects are in one-to-one correspondence with the conductive lines at the exposed platforms.