ADJUSTABLE DUTY CYCLE CIRCUIT

Techniques are disclosed for adjusting and programming the duty cycle of a signal generated by a circuit. In an embodiment, parallel transistors are coupled between a NAND gate and a supply voltage. Selectively enabling the parallel transistors adjusts the switching point of the NAND gate, thereby allowing control of the pulse width of the output signal. In an alternative embodiment, the size of the PMOS versus the NMOS transistors in the NAND gate is selectively varied to achieve the same effect. Further disclosed are applications of the techniques to calibrating the receiver to minimize measured second-order inter-modulation products and/or residual sideband.