Synchronous Rectifier Circuit Capable of Preventing Flow-Through Current

A synchronous rectifier circuit (DC-DC converter) (1) includes a CR integration circuit (23) and a discharge circuit (24). The CR integration circuit (23) outputs a voltage that varies at delayed timing as compared with a voltage induced in a secondary-side main winding (10B). The discharge circuit...

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Bibliographische Detailangaben
Hauptverfasser:	JINNOUCHI, TAKASHI, MIYAMOTO, HITOSHI
Format:	Patent
Sprache:	eng ; fre ; ger
Schlagworte:	APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC,OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWERSUPPLY SYSTEMS CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS,e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USERAPPLICATIONS CONTROL OR REGULATION THEREOF CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUTPOWER CONVERSION OR DISTRIBUTION OF ELECTRIC POWER ELECTRICITY GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS GENERATION TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINSTCLIMATE CHANGE
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Beschreibung
Zusammenfassung:	A synchronous rectifier circuit (DC-DC converter) (1) includes a CR integration circuit (23) and a discharge circuit (24). The CR integration circuit (23) outputs a voltage that varies at delayed timing as compared with a voltage induced in a secondary-side main winding (10B). The discharge circuit (24) discharges a gate voltage of a rectifier transistor (Q2) as a result of conduction of a discharge transistor (Q3) in response to the output voltage from the CR integration circuit (23). According to such a configuration, the rectifier transistor (Q2) is turned off earlier than the timing of switching of polarity of voltages induced in the secondary-side main winding (10B) and a secondary-side auxiliary winding (10C) in response to turn-on of a primary-side transistor (Q1).