HIGH-SPEED RECEIVER ARCHITECTURE

A receiver (e.g., for a 10G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-dependent impairments...

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Bibliographische Detailangaben
Hauptverfasser:	CARRER, HUGO, SANTIAGO, AGAZZI, OSCAR, ERNESTO, LUNA, GERMAN CESAR, AUGUSTO, CRIVELLI, DIEGO, ERNESTO, HUEDA, MARIO, RAFAEL, GRACE, CARL
Format:	Patent
Sprache:	eng ; fre ; ger
Schlagworte:	BASIC ELECTRONIC CIRCUITRY CODE CONVERSION IN GENERAL CODING DECODING ELECTRIC COMMUNICATION TECHNIQUE ELECTRICITY TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
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Beschreibung
Zusammenfassung:	A receiver (e.g., for a 10G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-dependent impairments. In one approach, the multi-channel equalizer is a feedforward equalizer (FFE) coupled to a Viterbi decoder, for example a sliding block Viterbi decoder (SBVD); and the FFE and/or the channel estimator for the Viterbi decoder are adapted using the LMS algorithm.