SEMICONDUCTOR ARRANGEMENT OF MOSFETS

The arrangement has metal oxide semiconductor field effect transistors (MOSFETs) (Q1-Q6) on a chip that has connections (10, 12, 14) and serving as power and control cells. Source and gate connections of the MOSFETs are connected with each other and contact connections (10, 14), respectively. A drai...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
1. Verfasser: CHABAUD, ANTOINE
Format: Patent
Sprache:eng ; fre ; ger
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:The arrangement has metal oxide semiconductor field effect transistors (MOSFETs) (Q1-Q6) on a chip that has connections (10, 12, 14) and serving as power and control cells. Source and gate connections of the MOSFETs are connected with each other and contact connections (10, 14), respectively. A drain connection of one power cell contacts the connection (12). Gate and drain connections of one control cell are connected with each other.