STORE INSTRUCTION ORDERING FOR MULTI-CORE PROCESSOR
A method and apparatus for minimizing stalls in a pipelined processor is provided. Instructions in an out-of-order instruction scheduler are executed in order without stalling the pipeline by sending store data to external memory through an ordering queue.
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| Hauptverfasser: | , , |
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| Format: | Patent |
| Sprache: | eng ; fre ; ger |
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| Zusammenfassung: | A method and apparatus for minimizing stalls in a pipelined processor is provided. Instructions in an out-of-order instruction scheduler are executed in order without stalling the pipeline by sending store data to external memory through an ordering queue. |
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