Power semiconductor packaging method and structure

A semiconductor chip packaging structure comprises a dielectric film (10) having one or more through holes (11) aligned with the one or more contact pads (22 and 23) of at least one power semiconductor chip (21). A patterned electrically conductive layer (40) adjacent to the dielectric film (10) has one or more electrically conductive posts (41) which extend through the one or more though holes (11) aligned with the contact pads (22 and 23) to electrically couple the conductive layer (40) to the contact pads (22 and 23). In certain embodiments, one or more air gaps may be formed between the dielectric film (10) and the active surface of the at least one power semiconductor chip (21). Methods for fabricating the semiconductor chip packaging structure are also disclosed.