Technique for reducing a parasitic DC bias voltage on a sensor

Technique for reducing a parasitic DC bias voltage on a sensor

A technique for reducing a parasitic DC bias voltage on a sensor (S1) monitors the parasitic DC bias voltage on a first element (10) of the sensor (S1). A controlled bias voltage that is applied between the first element (10) of the sensor (S1) and a second element (12) of the sensor (S1) is then mo...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: MOWERY, KENNETH D, TACKITT, DOUGLAS J
Format: Patent
Sprache:eng ; fre ; ger
Schlagworte:
INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIRCHEMICAL OR PHYSICAL PROPERTIES
MEASURING
PHYSICS
TESTING
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Beschreibung
Zusammenfassung:A technique for reducing a parasitic DC bias voltage on a sensor (S1) monitors the parasitic DC bias voltage on a first element (10) of the sensor (S1). A controlled bias voltage that is applied between the first element (10) of the sensor (S1) and a second element (12) of the sensor (S1) is then modified to substantially maintain the parasitic DC bias voltage at a desired potential.