LOW LEAKAGE AND DATA RETENTION CIRCUITRY

An integrated circuit (200) comprising: first circuitry (1000) configured to receive input signals, process the input signals, and retain data in a sleep state, the first circuitry including master latch circuitry (1010) and slave latch circuitry (1020); and sleep transistor circuitry (1042, 1044, 1046, and 1048) coupled to the first circuitry (1000) and configured to receive a sleep signal (SLEEPB) and to put the first circuitry into the sleep state when the sleep signal has a first value, wherein the first circuitry (1000) is configured to receive a clock signal (CK) and a hold signal (HOLDB), the hold signal (HOLDB) for causing the slave latch circuitry (1020) to retain the data while the rest of the first circuitry (1000) comes out of the sleep state, the first circuitry configured to come out of the sleep state in response to the sleep signal changing to a second value that is different from the first value.