Device and method for correcting errors in a processor with two processing units

A device for removing errors with a processor having two CPUs (dual-core), and in which the instructions redundant in both CPUs are processed. A division of the processor register in the first register and second register is undertaken, in which the first register is formed so that from it a specified state of the processor and the contents of the second register can be derived, whereby roll-back/back tracking devices are contained and are designed so that at least one instruction and/or the information in the first registers are rolled-back/back-tracked and carried out afresh and/or re-stored or re-established. An independent claim is included for a method for removing errors with a processor.