MASKING ARRANGEMENT AND METHOD FOR PRODUCING INTEGRATED CIRCUIT ARRANGEMENTS

A masking arrangement and method for producing integrated circuit. arrangements are described. The masking arrangement includes a substrate with lithographic patterns. The lithographic patterns are arranged in different partial regions for integrated circuits that have mutually different wiring of c...

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Bibliographische Detailangaben
Hauptverfasser:	STETTER, MICHAEL, FREUND, JOHANNES
Format:	Patent
Sprache:	eng ; fre ; ger
Schlagworte:	APPARATUS SPECIALLY ADAPTED THEREFOR BASIC ELECTRIC ELEMENTS CINEMATOGRAPHY ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY ELECTROGRAPHY HOLOGRAPHY MATERIALS THEREFOR ORIGINALS THEREFOR PHOTOGRAPHY PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES,e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTORDEVICES PHYSICS SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:	A masking arrangement and method for producing integrated circuit. arrangements are described. The masking arrangement includes a substrate with lithographic patterns. The lithographic patterns are arranged in different partial regions for integrated circuits that have mutually different wiring of components as well as for test patterns. Auxiliary patterns are provided for alignment of multiple lithography planes during production of one of the circuit arrangements either with or without simultaneous production of another of the circuit arrangement. The auxiliary patterns are arranged close to corners of each of the partial regions and contain alignment or overlap marks. The auxiliary patterns and the test pattern for a particular partial region form a frame around the partial region. Filling patterns are present between the partial regions.