Reconfigurable processor with configuration cache and semiconductor device

There is provided a processor that includes reconfigurable processing circuits (2a to 2d) for performing predetermined processing, in which a compiler is made capable of determining storage of configuration data in a cache (5). Configuration data (1) for defining a configuration of the processing circuits (2a to 2d) contains cache operation information defining an operation of the cache (5). A cache operation information acquisition section (3) acquires cache operation information from the configuration data when the configuration data is selected. A cache control section (4) controls the operation of the cache (5) storing the configuration data (1), based on the cache operation information. Since the cache operation information is contained in the configuration data, and the operation of the cache (5) storing the configuration data (1) is controlled based on the cache operation information, the compiler is capable of storing the cache operation information in the configuration data, based on a prediction on operations of a program.