Test structure for an electronic device and corresponding test method

A testing structure (1) for an electronic device is described, of the type comprising a first and second terminal (T1, T2) effective for providing impedance values of the testing structure (1), as well as an architecture (2) of distributed impedance elements (3-1, 3-2, ..., 3-N) associated with a pl...

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Bibliographische Detailangaben
Hauptverfasser:	D'URZO, VINCENZO, CASELLA, GIUSEPPINA, CINA', GIUSEPPE
Format:	Patent
Sprache:	eng ; fre ; ger
Schlagworte:	APPARATUS SPECIALLY ADAPTED THEREFOR BASIC ELECTRIC ELEMENTS CINEMATOGRAPHY ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY ELECTROGRAPHY HOLOGRAPHY MATERIALS THEREFOR MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES ORIGINALS THEREFOR PHOTOGRAPHY PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES,e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTORDEVICES PHYSICS SEMICONDUCTOR DEVICES TESTING
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Beschreibung
Zusammenfassung:	A testing structure (1) for an electronic device is described, of the type comprising a first and second terminal (T1, T2) effective for providing impedance values of the testing structure (1), as well as an architecture (2) of distributed impedance elements (3-1, 3-2, ..., 3-N) associated with a plurality of configurations of the device to be tested having different criticality levels and connected, in parallel with each other, between the first and second terminal (T1, T2). A testing method for an electronic device is also described, of the type comprising the steps of: providing a testing structure (1) comprising a first and second terminal (T1, T2) connected by means of an architecture (2) of distributed impedance elements; providing a plurality of configurations of the device to be tested having a different criticality; associating the plurality of configurations of the device to be tested with a plurality of impedance elements (3-1, 3-2, ..., 3-N) of the architecture (2) connected, in parallel with each other, to the first and second terminal (T1, T2); subjecting the configurations of the device to be tested to a testing step; measuring an impedance value (ZTOT) of the architecture (2) in correspondence with the first and second terminal (T1, T2); and calculating a highest criticality level of a configuration of the device to be tested being capable of overcoming the testing step on the basis of the measured impedance value (ZTOT).