ASIC CLOCK FLOOR PLANNING METHOD AND STRUCTURE
A method of designing a clock tree in an integrated circuit combines steps of making a list of all clock sinks; positioning a temporary reference insertion point (TIP); grouping the sinks together with structured clock buffers (SCBs) in a set of levels; and moving the SCBs to improve symmetry of the...
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| Format: | Patent |
| Sprache: | eng ; fre ; ger |
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| Zusammenfassung: | A method of designing a clock tree in an integrated circuit combines steps of making a list of all clock sinks; positioning a temporary reference insertion point (TIP); grouping the sinks together with structured clock buffers (SCBs) in a set of levels; and moving the SCBs to improve symmetry of the tree. The SCBs may be of several sizes and may be positioned horizontally or vertically and moved within limits to permit the program to calculate a complete tree. |
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