Digital frequency-upconverting circuit

An upconverting circuit [100] includes a polyphase component generator [101] that provides Np polyphase components at each input polyphase cycle, wherein Np>2 on each input polyphase cycle is defined by a clock. A memory [102] stores the polyphase components from at least one polyphase cycle prior to the current polyphse cycle. A plurality of filters [103-108] process the polyphase components stored in the memory [102]. Each filter processes a plurality of the polyphase components to generate a filtered polyphase component corresponding to that filter. A multiplexter [110] outputs the filtered polyphase components in a predetermined order to generate a filtered output signal. In one embodiment, each filter utilizes the same functional relationship to generate the filtered polyphase components. In another embodiment, the memory [102] is a shift register. The filters [103-108] can be of arbitrary complexity.