METHOD FOR FORMING A SEMICONDUCTOR DEVICE AND STRUCTURE THEREOF

METHOD FOR FORMING A SEMICONDUCTOR DEVICE AND STRUCTURE THEREOF

Dummy features (64, 65, 48a, 48b) are formed within an interlevel dielectric layer (36). Passivation layers (32 and 54) are formed by electroless deposition to protect the underlying conductive regions (44, 48a, 48b and 30) from being penetrated from the air gaps (74). In addition, the passivation l...

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Bibliographische Detailangaben
Hauptverfasser: LII, YEONG-JYH, T, SMITH, BRADLEY, P, YU, KATHLEEN, C, SOLOMENTSEV, YURI, E, SPARKS, TERRY, G, STROZEWSKI, KIRK, J, GOLDBERG, CINDY, K, FILIPIAK, STANLEY, M, FLAKE, JOHN, C
Format: Patent
Sprache:eng ; fre ; ger
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Zusammenfassung:Dummy features (64, 65, 48a, 48b) are formed within an interlevel dielectric layer (36). Passivation layers (32 and 54) are formed by electroless deposition to protect the underlying conductive regions (44, 48a, 48b and 30) from being penetrated from the air gaps (74). In addition, the passivation layers (32 and 54) overhang the underlying conductive regions (44, 48a, 48b and 30), thereby defining dummy features (65a, 65b and 67) adjacent the conductive regions (48a, 44 and 48b). The passivation layers (32 and 54) can be formed without additional patterning steps and help minimize misaligned vias from puncturing air gaps.