Address distribution among independent cache memories
A system (10) for transferring data to and from one or more slow-access-time-mass-storage nodes (12) which store data at respective first ranges of logical block addresses (LBAs), including a plurality of interim-fast-access-time nodes (20) which are configured to operate independently of one anothe...
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| Format: | Patent |
| Sprache: | eng ; fre ; ger |
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| Zusammenfassung: | A system (10) for transferring data to and from one or more slow-access-time-mass-storage nodes (12) which store data at respective first ranges of logical block addresses (LBAs), including a plurality of interim-fast-access-time nodes (20) which are configured to operate independently of one another. Each interim-fast-access-time node (20) is assigned a respective second range of the LBAs and is coupled to receive data from and provide data to the one or more slow-access-time-mass-storage nodes (12) within the respective second range. The system (10) further includes one or more interface nodes (26), which are adapted to receive input/output (10) requests from host processors (52) directed to specified LBAs and to direct all the IO requests to the interim-fast-access-time node to which the specified LBAs are assigned. |
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