Signal processing circuit module in which selection of clock signal is switched by simple means

A clock generation circuit (3) for generating an internal clock signal, a control section (2) that operates in accordance with a clock signal to be supplied, a signal processing circuit (4) that operates in accordance with the internal clock signal are arranged on a module substrate. An internal clock signal output terminal (5) connected to the clock generation circuit (3), and an external clock signal input terminal (6) connected to the control section (2) are extended from the module substrate (1). When the control section (2) is made to operate in accordance with the internal clock signal, the internal clock signal output terminal (5) is connected to the external clock signal input terminal (6), the internal clock signal is supplied to the control section (2) through the two connected terminals. When the control section is made to operate in accordance with an external clock signal, the external clock signal input to the external clock signal input terminal (6) is supplied to the control section (2).