Wiring layer fill structures

Semiconductor devices and manufacturing methods therefor are disclosed, in which conductive fill structures (30a, 30b, 30c, 30d) are provided in fill regions in an interconnect wiring layer between conductive wiring structures to facilitate planarization uniformity during metalization processing. One approach employs fill structures of varying sizes where smaller fill structures (30a) are formed near wiring regions (26a) having high aspect ratio wiring structures and larger fill structures (30d) are located near wiring regions (26d) with lower aspect ratio wiring structures. Another approach provides fill structures with varying amounts of openings, with fill structures having few or no openings being provided near low aspect r atio wiring structures and fill structures having more openings being located near higher aspect ratio wiring structures.