A content addressable memory (CAM) architecture providing improved speed

This invention provides a Content Addressable Memory (CAM) architecture providing improved speed by performing mutually exclusive operations in a first state of a clock cycle and by performing at least one operation, dependent on at least one previous operations, in a second state of the same clock cycles. The Content Addressable Memory (CAM) architecture (300) comprises an array of CAM cells (303) connected to a compare-data-write-driver (302) and to a read/write block (305), for receiving a compare-data and for reading and/or writing data in the array of CAM cells (303) respectively, outputs of the said CAM cells of said array (303) are coupled to a match block (304) providing match outputs signal lines that identifies a match/no-match at the end of a search operation, and a control logic for implementing search and address decoding operations during a first state and enabling read-or-write operations within a second state of the same clock cycle in the event of a match.