Microcontroller device for complex processing procedures and corresponding interrupt management process

In a microcontroller device in which complex processing procedures to be executed iteratively are implemented in a hardware manner, by means of finite state machines, which comprise a module for managing the processing procedures and an interrupt managing module, it is envisaged to provide a set of registers for enabling interruption of execution in the module for managing the processing procedures and transfer of control to the interrupt manager, as well as for enabling restoration of the control to the manager of the processing procedures. Said registers store information regarding the type of interrupt and the state on which it intervenes. Selection information is derived from the contents of said registers in order to establish whether the interrupt operates on a standard instruction or else on an iterative procedure and in order to command operation of the control unit accordingly.