AN ARRANGEMENT FOR ESD PROTECTION OF AN INTEGRATED CIRCUIT
To protect a high-frequency integrated circuit ( 1 ) against higher voltages than normal operating voltages on an input/output terminal connected to a bonding pad ( 2 ), a semiconductor varistor ( 3 ) having low and essentially constant resistance for said normal operating voltages and higher resist...
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Format: | Patent |
Sprache: | eng ; fre ; ger |
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Zusammenfassung: | To protect a high-frequency integrated circuit ( 1 ) against higher voltages than normal operating voltages on an input/output terminal connected to a bonding pad ( 2 ), a semiconductor varistor ( 3 ) having low and essentially constant resistance for said normal operating voltages and higher resistance for said higher voltages is integrated between the bonding pad ( 2 ) and the input/output terminal together with the integrated circuit ( 1 ). |
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