High-speed MOS-technology power device integrated structure, and related manufacturing process

A high-speed MOS-technology power device integrated structure comprises a plurality of elementary functional units formed in a lightly doped semiconductor layer (1) of a first conductivity type, the elementary functional units comprising channel regions (6) of a second conductivity type covered by a conductive insulated gate layer (8) comprising a polysilicon layer (5); the conductive insulated gate layer (8) also comprises a highly conductive layer (9) superimposed over said polysilicon (5) layer and having a resistivity much lower than the resistivity of the polysilicon layer (5), so that a resistance introduced by the polysilicon layer (5) is shunted with a resistance introduced by said highly conductive layer (9) and the overall resistivity of the conductive insulated gate (8) layer is lowered.