Synchronizing video formats with dissimilar timing

Synchronizing video formats with dissimilar timing

In order to synchronize two dissimilar video formats, two or more phase locked loop circuits (PLL's) may be used in tandem. A first PLL circuit (202) may be connected to the first video format (Master) and generate an intermediate frequency (262). A second PLL circuit (204) may use the intermed...

Ausführliche Beschreibung

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Bibliographische Detailangaben
1. Verfasser: NAEGLE, NATHANIEL DAVID
Format: Patent
Sprache:eng ; fre ; ger
Schlagworte:
ADVERTISING
ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICESUSING STATIC MEANS TO PRESENT VARIABLE INFORMATION
CRYPTOGRAPHY
DISPLAY
EDUCATION
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRICITY
PHYSICS
PICTORIAL COMMUNICATION, e.g. TELEVISION
SEALS
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Beschreibung
Zusammenfassung:In order to synchronize two dissimilar video formats, two or more phase locked loop circuits (PLL's) may be used in tandem. A first PLL circuit (202) may be connected to the first video format (Master) and generate an intermediate frequency (262). A second PLL circuit (204) may use the intermediate frequency as the timebase for generating the pixel clock (264) for the second video format (Slave). One or more Slaves may be connected to the generated pixel clock. The video synchronizing device may be a part of a graphics system, such as a graphics accelerator.