Correlated double sampling circuit and CMOS image sensor including the same

A correlated double sampling (CDS) circuit that reduces a shift in the potential of a node on the reference voltage side produced by reset operation is provided. A reset signal RST is turned to "H" and then is turned to "L". By doing so, a photodiode (D1) begins integration according to the intensity of light. This detected signal is sent to a CDS circuit (20). A switch SW1 and a connection switch for sampling (21) in the CDS circuit (20) are turned ON to accumulate the detected signal according to integration time in parallel capacitors C1 and C2 as electric charges. After a certain period of time has elapsed, the SW1 and connection switch for sampling (21) are turned OFF to hold the detected signal sampled. Next, the RST is turned again to "H" and the SW1 is turned ON. Then the RST is turned to "L" and the SW1 is turned OFF. By doing so, reset noise is sampled and held in the capacitor C1. As a result, a pure signal component can be extracted from the detected signal. After that a connection switch for outputting SW3 and a connection switch for reading (22) are turned ON to transfer an output voltage signal according to the signal component included in the detected signal to an output bus line.