Processor and method of pipelining

An electronic processing device has an integer pipeline (2) and a load/store pipeline (3) arranged in parallel to receive a series of instructions via a Fetch stage (4) and a Predecode stage (5). If an instruction (c) is stalled in a Decode stage (6) of the integer pipeline (2), one or more Delay stages (14, 15) can be switched into (and out of) the integer pipeline (2) between the Decode stage (6) and the Predecode stage (5) so as to increase or decrease its effective length. This allows the Predecode stage (5) to continue to issue instructions and therefore the load/store pipeline (3) does not need to stall. The maximum number of delay stages that need to be available for switching into the integer pipeline (2) is the same as the load-use penalty for that pipeline.