Receiver with three decision circuits

A receiver for high bitrate binary signals (DI) contains a soft decision circuit with three parallel deciders (D1-D3) coupled to a 2:1 multiplexer (M). The three deciders (D1-D3) have different threshold values and generate four potential states. The 2:1 multiplexer (M) translates the four different...

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Bibliographische Detailangaben
1. Verfasser:	WEDDING, BERTHOLD
Format:	Patent
Sprache:	eng ; fre ; ger
Schlagworte:	ELECTRIC COMMUNICATION TECHNIQUE ELECTRICITY TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
Online-Zugang:	Volltext bestellen
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Beschreibung
Zusammenfassung:	A receiver for high bitrate binary signals (DI) contains a soft decision circuit with three parallel deciders (D1-D3) coupled to a 2:1 multiplexer (M). The three deciders (D1-D3) have different threshold values and generate four potential states. The 2:1 multiplexer (M) translates the four different states into a restored data signal (DO) and a reliability signal (D1) indicating the decision reliability.