Anti-deciphering contacts

Anti-deciphering contacts and/or interconnection vias schemes for integrated devices, including the formation of a plurality of false contacts and/or false interconnection vias, intercepted as true contacts and true interconnection vias by lines patterned in a metallization layer deposited over an insulating dielectric layer or multilayer through which the true contacts and/or the true interconnection vias are formed. False contacts and false vias extending in the respective dielectric layer or multilayer for a depth insufficient to reach the active areas of a semiconductor substrate in the case of false contacts or structures of electrically conductive material defined in a layer of conductive material below said dielectric layer or multilayer in the case of interconnection vias.